Patent · US Active

Isolating a region of a system on a chip for safety critical operations

US11803668B2 · kind B2 · utility

0Cited by

13References

32Claims

0Family size

Assignee

NVIDIA Corporation · US

Inventors

Padam Patt Krishnani · Kanchinakote, IN
Avinash J V · Kanchinakote, IN
Anirban Ghosh · Bengaluru, IN
Phanikumar Parvatham · Hyderabad, IN
Vamshikrishna Yalamaddi · Kanchinakote, IN
Srinivasa Reddy Kalluri · Hyderabad, IN

Key dates

Filing date	Sep 16, 2021
Grant date	Oct 31, 2023
Priority date	—
Expiry date	Jan 7, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/3013
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In various examples, an integrated circuit includes first and second portions operating within separate domains. The second portion has an interface that connects the first and second portions. The second portion selectively locks the interface to prevent communication with the first portion over the interface, and selectively unlocks the interface to allow communication with the first portion over the interface.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.