Pic structure having barrier surrounding opening for optical element to prevent stress damage

US11804452B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Nicholas A. Polomoff · Irvine, US
• Jae Kyu Cho · Niskayuna, US
• Mohamed Rabie · Clifton Park, US
• Yunyao Jiang · Mechanicville, US
• Koushik Ramachandran · Beacon, US
• Pallabi Das · Kanchinakote, IN

Key dates

• Filing date: Jul 30, 2021
• Grant date: Oct 31, 2023
• Expiry date: Oct 18, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L25/167
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.