Interface circuit and operating method thereof to compensate for supply voltage variations
US11804841B2 · kind B2 · utility
1Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2022 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Jan 5, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.