High speed embedded protocol for distributed control system
US11804919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2023 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Jan 16, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Two or more modules communicate over a common control network including receiving by a message packet having data defined by a signal level at defined bit quanta of a bit, the defined bit quanta being less than every bit quanta of a bit, and the communication device samples bit quanta other than the defined bit quanta. The module receives signal disturbances and decodes the signal disturbances as having a value different from an expected value of the certain bit. In another form, the module uses a first counter based on a clock local to the communication device and a second counter having a higher sampling rate than the first counter. Here, the module receives over the control network a synchronizing portion of a message and counts clock ticks of the second counter over a portion of the message to determine a clock rate for a module that transmitted the message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.