Semiconductor devices
US11805639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2021 |
| Grant date | Oct 31, 2023 |
| Priority date | — |
| Expiry date | Oct 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.