Memory controlling device and memory system including the same
US11809317B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 24, 2022 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Feb 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controlling device configured to connect to a memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions including a first partition and a second partition is provided. A first controlling module accesses the memory module. A second controlling module determines whether there is a conflict for the first partition to which a read request targets when an incoming request is the read request, instructs the first controlling module to read target data of the read request from the memory module when a write to the second partition is in progress, and suspends the read request when a write to the first partition is in progress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.