Serial interrupt method, device, serial interrupt processing method, and processor
US11809350B2 · kind B2 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Jan 13, 2022 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Jan 30, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial interrupt method includes receiving a blank serial interrupt request signal (SerIRQ) and a level signal of a peripheral, based on the blank SerIRQ, generating an indication SerIRQ including an indication interrupt bit (IRQ_n) according to the level signal, and sending the instruction SerIRQ to a processor. The indication IRQ_n identifies the peripheral based on a binary code represented by a first level and a second level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.