Global modulo allocation in neural network compilation
US11809849B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Oct 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example, a method performed by a compiler comprises: receiving a dataflow graph of a neural network, the neural network comprising a neural network operator; receiving information of computation resources and memory resources of a neural network hardware accelerator intended to execute the neural network operator; determining, based on the dataflow graph, iterations of an operation on elements of a tensor included in the neural network operator; determining, based on the information, a mapping between the elements of the tensor to addresses in the portion of the local memory, and a number of the iterations of the operation to be included in a batch, wherein the number of the iterations in the batch are to be executed in parallel by the neural network hardware accelerator; and generating a schedule of execution of the batches of the iterations of the operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.