Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
US11809867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2020 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Sep 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed byte data elements; a second source register to store a second plurality of packed byte data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to concurrently multiply each of the packed byte data elements of the first plurality with a corresponding packed byte data element of the second plurality to generate a plurality of products; adder circuitry to add specified sets of the products to generate temporary results for each set of products; zero-extension or sign-extension circuitry to zero-extend or sign-extend the temporary result for each set to generate an extended temporary result for each set; accumulation circuitry to combine each of the extended temporary results with a selected packed data value stored in a third source register to generate a plurality of final results; and a destination register to store the plurality o…
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