Area-efficient dual-port and multi-port SRAM. area-efficient memory cell for SRAM

US11810615B2 · kind B2 · utility

Assignee

• XENERGIC AB · SE

Inventors

• Babak Mohammadi · Lund, SE
• Berta Morral Escofet · Oslo, NO
• Reza Meraji · Malmö, SE

Key dates

• Filing date: Mar 13, 2020
• Grant date: Nov 7, 2023
• Expiry date: Dec 4, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/419
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory cell has first, second, third and fourth transistors forming first and second cross-coupled inverters. The inverters define first and inverted first storage nodes; the first connected to first reference and first supply voltages, second connected to second reference and second supply voltages. A fifth transistor connected between first storage node and first bit line; sixth transistor connected between inverted first node and second bit line; first word line connected to fifth transistor, controlling access of first bit line to first node; second word line connected to sixth transistor, controlling access of second bit line to inverted first node. Relative voltage levels of first word line and first reference voltages, or first supply and first reference voltages, or second word line and second reference voltages, or second supply and second reference voltages, or first and second reference voltages are configured so first/inverted node are read/written independently.