Patent · US Active

Latch array with mask-write functionality

US11810636B2 · kind B2 · utility

0Cited by

6References

27Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Rui Li · San Diego, US
De Lu · Taipei, TW
Venkat Narayanan · San Diego, US

Key dates

Filing date	Jan 12, 2022
Grant date	Nov 7, 2023
Priority date	—
Expiry date	Jan 12, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2263
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.