Pixel array substrate
US11810923B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2023 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Feb 22, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.