Galvanic isolation circuitry and associated low power wakeup methods
US11811542B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2022 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Jun 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are methods, systems, and devices for providing galvanic isolation and low power wakeup of circuitry. According to one embodiment, an apparatus includes first isolation circuitry, second isolation circuitry, and first control circuitry. The first isolation circuitry includes a first primary interface and a first secondary interface. The first primary interface is galvanically isolated from the first secondary interface. The second isolation circuitry includes a second primary interface and a second secondary interface. The second primary interface is galvanically isolated from the second secondary interface. The first control circuitry is electrically coupled with the first secondary interface and the second secondary interface. The first control circuitry is configured to transition the apparatus from a sleep state to a wake state upon receiving a wake signal and the first isolation circuitry is configured to provide the wake signal to the first control circuitry via the first secondary interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.