Semiconductor devices including a liner and method of manufacturing the same
US11812607B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2022 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Mar 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.