Semiconductor device and manufacturing method thereof
US11812608B2 · kind B2 · utility
0Cited by
2References
20Claims
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Assignee
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Key dates
| Filing date | May 10, 2021 |
| Grant date | Nov 7, 2023 |
| Priority date | — |
| Expiry date | Aug 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.