Runtime configuration of chipset to support multiple I/O subsystem versions with one BIOS image
US11816491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2021 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Aug 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for configuring a peripheral bus of an information handling system performs, as part of a boot sequence, an initial configuration of a chipset setting pertaining to the bus based on a descriptor stored in a nonvolatile storage resource. After an operating system is loaded, a controller detects a peripheral device connecting to the bus and responds by performing a runtime configuration of the chipset setting based on capability information obtained from the peripheral device. The peripheral bus may comprise a USB pipe and a USB-C type connector, wherein the peripheral device is detected by a USB power delivery (PD) controller based on configuration channel (CC) pins of the USB-C connector. The PD controller may signal the chipset and send the device’s capability information to the chipset. The PD controller may assert a PMCALERT# signal of the chipset’s and send the capability information via a system management link (SMLink1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.