Memory device that performs erase operation to preserve data reliability
US11817153B2 · kind B2 · utility
1Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2021 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Oct 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.