Circuit for detecting anti-fuse memory cell state and memory
US11817159B2 · kind B2 · utility
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17References
16Claims
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Key dates
| Filing date | Aug 18, 2021 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Feb 24, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for detecting an anti-fuse memory cell state includes a current providing module connected to a first node and used to provide constant current; an anti-fuse memory cell array connected to the first node and including at least one bit line, the at least one bit line is connected to a plurality of anti-fuse memory cells and the first node; and a comparator, a first input end of the comparator is connected to the first node and a second input end of the comparator is connected to a first reference voltage, and used to detect a storage state of an anti-fuse memory cell to be tested in the anti-fuse memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.