Memory, memory test system, and memory test method
US11817166B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 2022 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Feb 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes: an input circuit, configured to: receive an outside clock signal, and output a first test clock signal; a test path selection circuit, connected to the input circuit, and configured to output a second test clock signal according to a read clock command; and an output circuit, connected to the test path selection circuit, and configured to convert the second test clock signal into a third test clock signal and output the third test clock signal to outside of the memory. In the embodiments of the disclosure, a time delay of inputting a clock signal into each chip under test is quantified, to acquire an actual output delay of the chip, thereby improving the accuracy of parallel tests of a plurality of chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.