Digital-to-analog converter (DAC) architecture optimization
US11817873B1 · kind B1 · utility
1Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | May 10, 2022 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | May 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/742
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-analog converter (DAC) comprises circuitry configured to generate, based on a mapping, L signals representing an N-bit digital input, wherein N and L are positive integers, and wherein N<L<2N−1, and circuitry configured to control current flow from L weighted current sources using the L respective signals, thereby generating an analog output that uniquely represents the N-bit digital input, wherein the weighted current sources have weights configured to minimize at least one error metric associated with the analog output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.