FPGA-based rate-adaptive spatially-coupled LDPC codes for optical communications
US11817879B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2020 |
| Grant date | Nov 14, 2023 |
| Priority date | — |
| Expiry date | Jun 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/616
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are systems, methods, and software for generating spatially-coupled low-density parity-check (SC-LDPC) codes. A method for generating SC-LDPC codes includes generating one or more quasi-cyclic low-density parity-check (QC-LDPC) codes, and also includes assigning at least one of the generated one or more QC-LDPC codes as one or more template codes. The method further includes copying at least a portion of the one or more template codes to introduce irregularity. The method also includes shifting one or more template codes on a sub-block basis to generate at least one SC-LDPC code. As compared to known LDPC code generation modalities, the disclosed invention provides a simplified technique for implementation in streamlined hardware which has more general applicability across both present, and anticipated, communication systems, including those adapted for use with optical communications, wireless communications, and 5G as well as future 6G.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.