Patent · US Active

Network switch with DMA controller for independent direct memory access of host system

US11822494B2 · kind B2 · utility

0Cited by

5References

24Claims

0Family size

Assignee

MARVELL ASIA PTE LTD · SG

Inventors

Manfred Kunz · Berlin, DE
Markus Althoff · Achern, DE
Xiongzhi Ning · Karlsruhe, DE

Key dates

Filing date	Jul 11, 2022
Grant date	Nov 21, 2023
Priority date	—
Expiry date	Jul 11, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/4022
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A network switch includes a data bus, a register, an endpoint controller and a direct memory access controller. The endpoint controller is configured to receive a descriptor generated by a device driver of a host system, store the descriptor in the register, and transfer data between a root complex controller of the host system and the data bus. The descriptor identifies an address of a buffer in a memory of the host system. The direct memory access controller is configured to receive the address of the buffer from the endpoint controller or the register and, based on the address and an indication generated by the device driver, independently control transfer of the data between the memory of the host system and a network device connected to the network switch. The direct memory access controller is a receive direct memory access controller or a transmit direct memory access controller.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.