Dynamic refresh rate control
US11823728B2 · kind B2 · utility
0Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Mar 4, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.