System and method for data integrity in memory systems that include quasi-volatile memory circuits
US11823760B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 27, 2021 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Oct 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes: (a) a memory array including numerous quasi-volatile (“QV”) memory units each configured to store a first portion of a code word encoded using an error-detecting and error-correcting code (“ECC-encoded code word”); (b) a refresh circuit for reading and writing back the first portion of the ECC-encoded code word of a selected one of the QV memory unit; (c) a global parity evaluation circuit configured to determine a global parity of the ECC-encoded code word of the selected QV memory unit; and a memory controller configured for controlling operations carried out in the memory array, wherein when the global parity of the ECC-encoded code word of the selected QV memory unit is determined at the global parity evaluation circuit to be a predetermined parity, the memory controller (i) performs error correction on the selected ECC-encoded code word and (ii) causes the first portion of the corrected ECC-encoded code word to be written back to the selected QV memory unit, instead of the refresh circuit writing back the first portion of the ECC-encoded code word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.