Memory system and memory access interface device thereof
US11823770B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2022 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Aug 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.