Semiconductor package and method of manufacturing the semiconductor package
US11824045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2021 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Jan 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first, second, third and fourth semiconductor chips sequentially stacked on one another. The second semiconductor chip includes a second substrate and a second substrate recess formed in an edge of a backside surface of the second substrate. The third semiconductor chip includes a third substrate and a first metal residual material provided in a peripheral region of a front surface of the third substrate. When the second semiconductor chip and the third semiconductor chip are bonded to each other such that the front surface of the third substrate and the backside surface of the second substrate face each other, the first metal residual material is located in the second substrate recess. A first bonding pad on the backside surface of the second substrate and a second bonding pad on the front surface of the third substrate are bonded to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.