Method of fabricating super-junction based vertical gallium nitride JFET and MOSFET power devices
US11824086B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2022 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Dec 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30617
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.