Low latency, broadband power-domain offset-correction signal level circuit implementation
US11824530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2022 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Apr 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0175
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interface circuit may convert an input electrical signal at an input node in a first power domain having a first ground or reference voltage into an output electrical signal at an output node in a second power domain having a second ground or reference voltage. Notably, a level-shifting circuit in the interface circuit may selectively electrically couple to the input node and the output node. Then, when there is electrical coupling, the level-shifting circuit may perform level shifting between the first power domain and the second power domain. The level shifting may involve: passing, using a first filter, frequencies in the input electrical signal below a first corner frequency; passing, using a second filter in parallel with the first filter, frequencies in the input electrical signal above a second corner frequency; and combining outputs of the first filter and the second filter as the output electrical signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.