Error correction using soft decision bits and multiple hypotheses
US11824556B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2022 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | Jul 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for error correction based on soft decision bits and multiple hypotheses includes: maintaining a plurality of previous single bit-flip hypotheses, each hypothesis including a respective bit-flip, a respective pre-flip bit confidence, and a respective hash responsive to the respective bit-flip; receiving a bit and a corresponding bit confidence; comparing the received bit confidence with a highest pre-flip bit confidence of the maintained plurality of single bit-flip hypotheses; and if the received bit confidence is less than the highest pre-flip bit confidence, forming a new single bit-flip hypothesis and replacing a prior bit-flip hypothesis having the highest pre-flip bit confidence with the new hypothesis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.