Memory cell, 3D memory and preparation method therefor, and electronic device
US11825642B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2023 |
| Grant date | Nov 21, 2023 |
| Priority date | — |
| Expiry date | May 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell, a 3D memory and a preparation thereof, and an electronic device. The memory cell includes a first transistor and a second transistor disposed on a substrate, the first transistor includes a first gate, a first electrode, a second electrode and a first semiconductor layer disposed on the substrate; the second transistor includes a third electrode, a fourth electrode, a second gate extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding a sidewall of the second gate which are disposed on the substrate, the second semiconductor layer includes a second source contact region and a second drain contact region arranged at intervals, a channel between the second source contact region and the second drain contact region is a horizontal channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.