Systems, apparatus, and methods to debug accelerator hardware
US11829279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2021 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Jan 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.