Memory system, method of operating the same and storage device using the same
US11829633B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2021 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Nov 20, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory controller and M memory chips. The memory controller generates a first data signal having one of 2M voltage levels different from each other, where M is a natural number greater than or equal to two, and outputs the first data signal through a first channel. The first data signal represents first data including M bits. The M memory chips are commonly connected to the memory controller through the first channel. When the M memory chips have an enabled state, the M memory chips simultaneously receives the first data signal transmitted through the first channel from the memory controller, and simultaneously obtains the M bits included in the first data based on the first data signal. Each of the M memory chips obtains a respective one of the M bits, and operates based on the respective one of the M bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.