Memory controller system and a method of pre-scheduling memory transaction for a storage device

US11829643B2 · kind B2 · utility

Assignee

• SKYECHIP SDN BHD · MY

Inventors

• Chee Hak Teh · Kampung Bukit Kechil, MY
• Yu Ying Ong · Ampang Jaya, MY
• Weng Li Leow · Bayan Lepas, MY
• Muhamad Aidil Jazmi · Bayan Lepas, MY

Key dates

• Filing date: Dec 27, 2021
• Grant date: Nov 28, 2023
• Expiry date: Apr 8, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F3/0673
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.