Static block frequency prediction in irreducible loops within computer code
US11829738B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2021 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Apr 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A block frequency of a block in an irreducible loop in computer code is statically determined. The statically determining includes splitting an incoming block mass among multiple loop headers of the irreducible loop to provide an initial mass for the block. A bottom-up traversal and a top-down traversal of a plurality of loops of the computer code including the irreducible loop are iteratively performed to update a mass of the block. The iteratively performing commences with propagating the initial mass of the block to one or more blocks of one or more loops of the plurality of loops and continues with propagating and updating masses of select blocks of the plurality of loops until a predefined point is reached providing a resulting mass for the block. The block frequency of the block is determined using the resulting mass and is to be used in processing associated with the computer code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.