Instruction driven dynamic clock management for deep pipeline and out-of-order operation of microprocessor using on-chip critical path messenger and elastic pipeline clocking
US11829769B2 · kind B2 · utility
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Key dates
| Filing date | Dec 18, 2019 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Nov 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and/or methods can include techniques to exploit dynamic timing slack on the chip. By using a special clock generator, the clock period can be shrunk as needed at every cycle. The clock period is determined during operation by checking “critical path messengers” to indicate how much dynamic timing slack exists. Elastic pipeline timing can also be introduced to redistribute timing among pipeline stages to bring further benefits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.