Digital processing systems and methods for managing sprints using linked electronic boards
US11829953B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2022 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Dec 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F40/295
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and computer-readable media for managing a plurality of sprints using a plurality of electronically linked boards are disclosed. A low-level board with rows and columns is generated, containing sprint-related function data associated with the plurality of sprints. At least one internal column and at least one external column are generated on the low-level board, for linking to an associated high-level board. Group-by controls are presented, and in response to activation of an internal control, rows on the low-level are organized board into first groups based on common internal column data. In response to activation of the external control, rows on the low-level board are reorganized into second groups by common external column data. Links to the at least one associated high-level board are accessed on the low-level board, and data from the at least one associated high-level board is extracted and imported onto the low-level board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.