Readout circuit, memory, and method of reading out data of memory
US11830569B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 12, 2023 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Jan 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a readout circuit, a memory, and a method of reading out data of a memory. The readout circuit includes: a sense amplifier and an isolation unit, the sense amplifier being connected to a bit line and a complementary bit line through the isolation unit, the bit line being connected to a memory cell and the complementary bit line being connected to a memory cell, and the isolation unit being configured to disconnect the sense amplifier from the bit line and the complementary bit line in response to an isolation signal; and an offset canceling unit, configured to perform an offset cancellation on the sense amplifier in response to an offset canceling signal, at least a part of a stage of a charge sharing being performed at the same time as at least a part of a stage of an operation of the offset canceling unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.