Patterned nanochannel sacrificial layer for semiconductor substrate reuse
US11830733B2 · kind B2 · utility
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Key dates
| Filing date | Mar 28, 2022 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Mar 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7806
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described herein are systems and methods of utilizing nanochannels generated in the sacrificial layer of a semiconductor substrate to increase epitaxial lift-off speeds and facilitate reusability of GaAs substrates. The provided systems and methods may utilize unique nanochannel geometries to increase the surface area exposed to the etchant and further decrease etch times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.