Integrated circuits and methods for forming integrated circuits
US11830788B2 · kind B2 · utility
1Cited by
1References
6Claims
0Family size
Assignee
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Key dates
| Filing date | May 25, 2021 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Sep 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.