Semiconductor devices including power connection lines
US11830813B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2021 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Oct 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip includes a first core region including a first core and a first power line configured to provide a first voltage to the first core, a second core region including a second core and a second power line configured to provide the first voltage to the second core, a cache region between the first core region and the second core region, the cache region including a cache and a third power line providing a second voltage to the cache, and arranged between the first core region and the second core region; and a first power connection line connecting the first power line to the second power line and arranged in the cache region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.