Backside integrated voltage regulator for integrated circuits
US11830855B2 · kind B2 · utility
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2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2022 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Feb 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.