Stress reduction on stacked transistor circuits
US11831309B2 · kind B2 · utility
1Cited by
19References
19Claims
0Family size
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Key dates
| Filing date | Apr 9, 2019 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Apr 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.