Level shifting circuit and method
US11831310B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 8, 2022 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Aug 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a first power supply node configured to have a first power supply voltage level, a second power supply node configured to have a second power supply voltage level separate from the first power supply voltage level, an n-well, a bias circuit, and a level shifter. The n-well contains first and second PMOS transistors including first source/drain (S/D) terminals coupled to the first power supply node, and third and fourth PMOS transistors including second S/D terminals coupled to the second power supply node. The bias circuit includes the first PMOS transistor including a third S/D terminal coupled to the n-well and a gate coupled to the second power supply node, and the third PMOS transistor including a fourth S/D terminal coupled to the n-well and a gate coupled to the first power supply node. The level shifter includes the second and fourth PMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.