Readout circuit, offset voltage eliminating method, computer device, and storage medium
US11831319B2 · kind B2 · utility
0Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2022 |
| Grant date | Nov 28, 2023 |
| Priority date | — |
| Expiry date | Apr 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/16
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are a readout circuit, an offset voltage eliminating method and device, a computer device, and a non-transitory computer-readable storage medium. The readout circuit includes an object quantizer and an offset voltage elimination circuit. The offset voltage elimination circuit includes a correction circuit and a calibration circuit, an input of the correction circuit is connected to an output of the object quantizer, a compensation input of the calibration circuit is connected to an output of the current compensator, and a reference input of the calibration circuit is connected to the output of the object quantizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.