Circuit and method to measure simulation to silicon timing correlation
US11835580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2021 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Aug 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/134
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.