System and method of utilizing memory medium fault resiliency with secure memory medium portions
US11836514B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2021 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Mar 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45587
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may receive a request for a secure memory region with fault resiliency from first processor instructions being executed at a first processor privilege level; allocate a first enclave, in which the first enclave protects at least one of second processor instructions and data from being read by and from being altered by third processor instructions executing at a second processor privilege level; allocate a second enclave, in which the second enclave protects the at least one of the second processor instructions and the data from being read by and from being altered by the second processor instructions; store the at least one of the second processor instructions and the data in the first enclave; and mirror the at least one of the second processor instructions and the data in the second enclave.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.