Storage subsystem read voltage determination system
US11837306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2022 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Apr 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage subsystem read voltage determination system coupled to a first storage subsystem may read data from the first storage subsystem at a plurality of different read voltage sets and, for each of the plurality of read voltage sets, generate a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem. The storage subsystem read voltage provisioning system also generates an error correction capability graph associated with error correction code used by the first storage subsystem and, based on the bit error probability distributions and the error correction capability graph, generates a respective average codeword error rate for each of the plurality of read voltage sets. The storage subsystem read voltage provisioning system then identifies a first read voltage set for which a minimum average codeword error rate was determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.