Multi-port memory device and a method of using the same
US11837319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2020 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Mar 7, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.