Structure including transistor using buried insulator layer as gate dielectric and trench isolations in source and drain

US11837605B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Tom Herrmann · Dresden, DE
• Zhixing Zhao · Dresden, DE
• Alban Zaka · Dresden, DE
• Yiching Chen · San Jose, US

Key dates

• Filing date: Dec 17, 2021
• Grant date: Dec 5, 2023
• Expiry date: Dec 17, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.