Semiconductor device and manufacturing method therefor
US11837633B2 · kind B2 · utility
0Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2022 |
| Grant date | Dec 5, 2023 |
| Priority date | — |
| Expiry date | Mar 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The barrier layer comprises a doped semiconductor region extending from a top surface to a bottom surface of the barrier layer and located between the drain and the gate conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.